Wireless communications systems are ubiquitous in today's world. Cellular telephones and wireless personal digital assistants (PDAs) configured in cellular networks provide mobility and afford users the ability to communicate over vast distances without the obtrusiveness and physical limitations presented by wired communications systems. Laptop computers equipped with wireless network interface cards in wireless local area networks (WLANs), and peripheral devices such as wireless keyboards and wireless mice configured in wireless personal area networks (WPANs), also provide users with greater mobility and freedom of movement compared to wired networking approaches.
FIG. 1 is a simplified block diagram of a typical prior art radio frequency (RF) wireless communications transmitter 100. The communications transmitter 100 includes a baseband processor 102, an RF upconverter 104, a power amplifier 106, and an antenna 108. These components are common to most every modern RF transmitter, whether the transmitter is designed for use in a WLAN, a WPAN or a wide area network (WAN) such as a cellular communications network. The baseband processor 102 operates to generate modulation data from an incoming digital message. The RF upconverter 104 uses modulation data to modulate an RF carrier signal. The modulated RF carrier signal is then amplified by the PA 106 and radiated by the antenna 108 to a remote receiver.
To reduce size and conserve power, the various components of the RF transmitter 100 are often implemented in the form of several integrated circuits (ICs). Typically, as shown in FIG. 2, the baseband processor is implemented in a first IC 202, while the upconverter 104 and PA 106 are formed in second and third ICs 204 and 206. The upconverter 104, in particular, is normally integrated with other analog components on second IC 204, which is commonly referred to in the art as the “RFIC” 204.
Modulation data generated by the baseband IC 202 is provided to the RFIC 204 over a data bus 208. A control interface 210 is also included between the baseband IC 202 and RFIC 204, to provide a means over which the baseband IC 202 can control events and timing of the RFIC 204, and to provide a means for sending control parameters that set or adjust the operation of components on the RFIC 204. Unfortunately, this control mechanism is slow since the control signals and control parameter data must be sent from one chip to another. Delays also result if the control parameter data must be first retrieved from off-chip memory before it is sent over the interface 210 to the RFIC 204. All of these delays in control are exacerbated by the fact that the control interface 210 is usually, for historical reasons, implemented as a serial interface (often referred to in the art as a serial port interface (or “SPI”)).
Delays in control are undesirable since they result in transmission delays. While transmission delays may be tolerable in some low speed applications, in others they are not, particularly in wideband applications that have corresponding high data rates. Delays can also be particularly problematic in transceiver technologies requiring a high degree of control and calibration such as, for example, polar modulation transmitters.
It would be desirable, therefore, to have methods and apparatus for controlling events and operational characteristics of wireless communications systems which avoid the control and transmission delay problems experienced by prior art wireless communication systems.